Association for Computing Machinery
As the technology moves into the nano-realm, traditional Single-Error-Correcting, Double-Error-Detecting (SEC-DED) codes are no longer sufficient for protecting memories against transient errors due to the increased multi-bit error rate. The well known Double-Error-Correcting (DEC) BCH codes and the classical decoding method for BCH codes based on Berlekamp-Massey algorithm and Chien search cannot be directly adopted to replace SEC-DED codes because of their much larger decoding latency. In this paper, the authors propose the Hierarchical Double-Error-Correcting (HDEC) code. The construction methods and the decoder architecture for the codes are described.