University of California
In this paper, the authors proposes a new model of functional units for variation-induced timing errors due to PVT variations and device Aging (PVTA). The model takes into account PVTA parameter variations, clock frequency and the physical details of Placed-and-Routed (P&R) functional units in 45nm TSMC analysis flow. Using this model and PVTA monitoring circuits, they propose Hierarchically Focused Guardbanding (HFG) as a method to adaptively mitigate PVTA variations. They demonstrate the effectiveness of HFG on GPU architecture at two granularities of observation and adaptation: fine-grained instruction-level; and coarse-grained kernel-level.