Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

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Provided by: edaa
Format: PDF
Multiple levels of design hierarchy are common in current-generation System-On-Chip (SOC) integrated circuits. However, most prior work on Test Access Mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. The authors investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider.
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