High Density Four-Transistor SRAM Cell with Low Power Consumption
In this paper, the authors present a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional six-transistor cell using same design rules. Also, proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell and write operation perform from another side of cell and swing voltage reduced on word-lines thus power during read/write operation reduced.