High-Endurance and Performance-Efficient Design of Hybrid Cache Architectures through Adaptive Line Replacement

Provided by: Institute of Electrical & Electronic Engineers
Topic: Storage
Format: PDF
In this paper, the authors propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, they assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation.

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