Journal of Semiconductor Technology and Science (JSTS)
In this paper, the authors propose column-parallel three step Single Slope Analog-to-Digital Converter (SSADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step, SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SSADC. The proposed three steps SS-ADC have a 12-bit resolution and 200kS/s at 25 MHz clock frequency.