High-Level Simulations of On-Chip Networks
Network-on-Chip (NoC) has been proposed as a new design methodology to cope with these problems. NoCs consist of heterogeneous resources that are encapsulated from another which allows the use of different voltages, frequencies or even diverse technologies for each resource. Furthermore, encapsulation eases the exchange and reuse of resources as well as the integration of intellectual property (i.e. predefined macro blocks). The independent resources are connected (by a determined interface) to an on-chip network which affords the communication among the resources whereas the network consists of routers and physical links.