High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
As Very Large Scale Integration (VLSI) process technology continues to scale down transistor sizes, modern computing devices are becoming extremely complex. In order to face this complexity explosion, the shifting of design methodologies towards higher level of abstraction has been proposed. This high level view of the design procedure enables the automated synthesis of applications' architecture that is written in an application-level description i.e. C/C++. Additionally, it allows designers to explore the tradeoffs between different system and implementation parameters to conclude in an efficient design solution.