Provided by:
Imperial College London
Topic:
Big Data
Format:
PDF
High-level synthesis promises a significant shortening of the FPGA design cycle when compared with design entry using Register Transfer Level (RTL) languages. Recent evaluations report that C-to-RTL flows can produce results with a quality close to hand-crafted designs. Algorithms which use dynamic, pointer-based data structures, which are common in software, remain difficult to implement well. In this paper, the authors describe a comparative case study using Xilinx Vivado HLS as an exemplary state-of-the-art high-level synthesis tool. Their test cases are two alternative algorithms for the same compute-intensive machine learning technique (clustering) with significantly different computational properties.
