High Performance Adder Circuit in VLSI System
In VLSI system, the integrated circuit design has important role. The various parameters are considering for design the circuit. The important parameters are power and delay. The different tools are used to perform the operation. However, here the combinational circuit (i.e. adder) designed by using different logic. The domino logic is the base of the proposed method. PMOS Pull Up Network (PMOS PUN) is used to perform the operation. The proposed method includes the tradeoff of the power and delay. It designed by using tanner EDA tool with 1V power supply and 0.5MHz frequency.