High Performance CMOS Four Quadrant Analog Multiplier in 45 nm Technology

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Provided by: International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Topic: Hardware
Format: PDF
In this paper, a compact low-voltage CMOS analog multiplier is proposed. It is based on the square-law characteristics of the MOS transistor. The proposed circuit is obtained by rearranging circuit topology of a recently reported multiplier which is unpractical since the circuit topology itself needs an ideal voltage reference to form a multiplication function. By doing so, the ideal voltage reference is no longer required leading to achieve a new multiplier circuit with real compactness. Simulated results using TSPICE for 0.045 CMOS process show that main performances of the proposed modulator including power consumption, noise, delay and bandwidth are successfully improved.
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