High Performance Low Power Dynamic Multiplier

Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE)
Topic: Hardware
Format: PDF
The DPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power education. in this paper, the authors provide the experience of applying an advanced version of their former Dynamic Power Suppression Technique (DPST) on multipliers for high-speed and low-power purposes. To filter out the use-less switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition.

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