The majority of logic systems are based on the synchronous principle because of design simplicity using discrete time, which avoids the hazards. On the other side there are problems with global clock distribution, which leads to skew problem. Asynchronous design provides a platform to overcome the drawback of synchronous design such as global worst-case latency, clock distribution and skew problem. In the VLSI design area, power and speed are the major factors to be considerable. So, in order to improve the speed the authors have to concentrate on delay. In this paper, an asynchronous ALU is designed using a Muller C-element concept to reduce delay in the circuit.