Dr.B.R Ambedkar National Institute of Technology
Recently several high-speed, high-resolution CMOS pipelined A/D converters with the operational frequency up to MHz have been reported. In high speed ADC, speed limiting element is comparator. This paper describes a very high speed and low offset preamplifier-latch comparator. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are good. Based on TSMC 0.18um CMOS process model, simulated results show the comparator can work under ultra-high speed clock frequency 1GHz.