High Speed and Low Power Implementation of FIR Filter Design Using DADDA & WALLACE Tree Multiplier
The most area consuming arithmetic operations in high-performance circuit’s Finite Impulse Response (FIR) multiplication is one. The authors are using different types of multipliers to reducing the cost of effective parameters in FIR filter design. They use only truncated multipliers in design, by using these multipliers they consume some more area and power, and ineffective results in transposed form. The structural adders and delay elements occupies more area and consumes power in these form so it was a reason to forward the proposed method.