High Speed and Low Power Multiplier Using Reversible Logic for Wireless Communications

Provided by: Creative Commons
Topic: Enterprise Software
Format: PDF
Multipliers are vital components of any processor or computing machine, performance of microcontrollers and digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation.

Find By Topic