High Speed Cycle Approximate Simulation for Cache-Incoherent MPSoCs
The authors present a new high speed cycle-approximate simulator, addressing an important, neglected category of multicore systems: deeply-embedded cache-incoherent MPSoCs. They take advantage of the unique properties of these systems to increase the parallelism of the simulation. They achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. They present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average they simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case.