High Speed, Low Offset, Low Power, Fully Dynamic CMOS Latched Comparator
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple design of three stages is represented. The basic disadvantages of latch type comparators are overcome by producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power consumption is reduced to 450uW. It is designed for 1.8VDC supply voltage and 1MHz clock frequency for PVT variations. The simulation of the comparator is done in cadence virtuoso analog design environment using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage.