International Journal of Innovative Science Engineering and Technology (IJISET)
Carry SeLect Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. By gate level modification of CSLA architecture the authors can reduce area. Based on this modification 16-b SQuare-RooT CSLA (SQRT CSLA) architecture have been developed. The proposed design has reduced area as compared with the regular SQRT CSLA. This paper evaluates the performance of the proposed designs in terms of area and delay through Xilinx ISE 14.7 (VHDL). In here both regular and modified carry select adder is used in a wallace tree and booth multiplier and done FPGA implementation using Spartan-3.