High Speed Power Efficient Static Single Edge Triggered Storage Element with Reduced Clocked Transistors
In this paper, the authors propose a new high performance and power efficient static single-edge triggered clocked storage element. In this paper, comparative analysis of two existing flip-flop designs along with the proposed design is made. Among all flip-flops compared, the proposed flip-flop consumes the lowest power when input is idle having up to 70.44% improvement in average power consumption and the second lowest power for other data activities. The proposed flip-flop shows the shortest delay having up to 34.66% improvement in delay and the lowest PDP having up to 37.22% improvement in PDP.