High Speed RC4 Algorithm based on True Dual Port RAM by using Verilog HDL
In this paper, the authors present high speed hardware implementation and an area efficient of the RC4 algorithm based on True Dual Port (TDP) RAM. The proposed architecture uses Block RAM (BRAM) implementation to reduce the area and to increase the speed of operation hence throughput. The proposed design uses only one 256 bytes True Dual Port RAM for key stream generation and it needs two clock cycles per one byte. It supports 1 byte to 256 bytes of variable key length and it achieves 71.39 MB/s throughput at 142.78 MHz maximum operating frequency.