High Speed Reverse Converter Design via Parallel Prefix Adder Based Multiplier

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Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors propose the design of reverse converter using parallel prefix adder based multiplier for residue number system. Now-a-days, the parallel prefix adders are not used even though it provides significant delay reduction and high speed operation because of higher power consumption. The novel specific hybrid parallel prefix adder components that compensate the delay and power consumption in the existing system are applied to design the reverse converter. Different parallel adder structures are analyzed among that the Brent-kung prefix network is used for the parallel prefix addition because of the minimum fan-out.
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