The speed of a multiplier is of utmost importance to any Digital Signal Processor (DSP). Along with the speed its precision also plays a major role. Although, floating point multipliers provide required precision they tend to consume more silicon area and are relatively slower compared to fixed point (Q-format) multipliers. In this paper, the authors propose a method for fast fixed point signed multiplication based on Urdhava Tiryakbhyam method of Vedic mathematics. The coding is done for 16-bit (Q15) and 32-bit (Q31) fractional fixed point multiplications using Verilog and synthesized using Xilinx ISE version 12.2.