In this paper, the authors are to design a parallel counter architecture with high operating frequency and wide range. That is achieved by partitioning the entire structure into two main parts Counting Portion (CP) and State Look-ahead Portion (SLP). The CP is partitioned to smaller bit counting sections separated by D-FF. The SLP is partitioned same way as CP. The Verilog Hardware Description Language is used for modeling the architecture. The results obtained by the synthesize tool Xilinx ISE 12.4i on a SPARTAN 3E chip demonstrate that Parallel Counter Architecture (PCA) have improved operating frequency as compared to conventional synchronous counter.