High Throughput and Low Power Enhancements for LDPC Decoders

Modern VLSI decoders for Low-Density ParityCheck (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible footprint. In this paper, the authors present two optimizations to enhance the throughput and reduce the power consumption for these decoders. As a first optimization, they seek to speedup the decoding task by modifying the processing step known as syndrome check. They partition this task and perform it in on-the-fly fashion. As a second optimization, they address the topic of iteration control in order to save energy and time on unnecessary decoder operation when processing undecodable blocks. They propose an iteration control policy that is driven by the combination of two decision metrics.

Provided by: EURECOM Topic: Mobility Date Added: Nov 2011 Format: PDF

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