Carnegie Mellon University
Energy consumption and design simplicity are paramount concerns in on-chip interconnects for Chip Multi-Processors (CMPs). Several proposed and a few implemented many-core on-chip interconnects are mesh or torus-based. These designs offer good scalability. However, most mainstream commercial Chip Multi-Processors (CMPs) use rings, in which each network node has relatively simpler ring stop logic. Network traffic injected into the ring continues until reaching its destination, so no flow control or buffering is needed, unlike a mesh. This design simplicity is attractive to implementers of small-to-medium-scale CMPs, and at lower core counts, rings can offer competitive performance with lower die area and energy consumption.