The University of Tulsa
As technology scales and processor speeds improve, power has become a first-order design constraint in all aspects of processor design. In this paper, the authors explore the use of criticality metrics to reduce dynamic and leakage energy within data caches. They leverage the ability to predict whether an access is in the application's critical path to partition the accesses into multiple streams. Accesses in the critical path are serviced by a high-performance cache bank. Accesses not in the critical path are serviced by a lower energy cache bank.