Flexible, high performance Network-on-Chip (NoC) is of paramount importance for the upcoming multi core era relying on extremely parallel computing. The NoC frameworks that currently exist target System-on-Chip (SoC) applications and are not perfectly suited for Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA) implementations. Such implementations which include e.g. Multicore graphic processing units or coprocessors show different characteristics compared to SoCs and demand for a novel solution. They are much more latency sensitive and require a tight integration of the switch into the processing pipeline while maintaining flexibility and generality.