Hybrid Electric/Photonic Networks for Scientific Applications on Tiled CMPs

Provided by: UC AB
Topic: Hardware
Format: PDF
As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that the gains in speed not come with increasingly high energy consumption. Recent advances in 3D Integration (3DI) CMOS technology have made possible hybrid photonic Networks-on-Chip (NoC), which have the potential to result in high performance while consuming much less power than an equivalent electrical network. However, it remains to be seen whether the benefits of hybrid NoCs will carry over for real applications.

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