Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Provided by: edaa
Topic: Hardware
Format: PDF
The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories. A good interconnect design plays a key role in improving the performance of such systems. In this paper, the authors introduce a hybrid communication infrastructure using both the standard bus and their area-efficient and delay-optimized Network-on-Chip (NoC) for heterogeneous multicore systems, especially hardware accelerator systems. An adaptive data communication-based mapping for reconfigurable hardware accelerators is proposed to obtain a low overhead and latency interconnect.

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