Hybrid Routers for Wireless Network on Chip (NoC) Design

Provided by: International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
Topic: Hardware
Format: PDF
The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In real-time applications there are different communication needs among the cores. When NoCs (Networks on Chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution.

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