IdlePower: Application-Aware Management of Processor Idle States

Provided by: Georgia Institute of Technology
Topic: Hardware
Format: PDF
Power has become the first class design constraint in modern processor design. To reduce the power density caused by aggressive, speculative execution seen in previous processor generations, computer architects have turned to a multi-core design strategy with each core substantially simplified. Additionally, different power-saving features have been pro-posed and integrated into each core to adapt dynamic execution scenarios. Due in part to the independent nature of these cores, the power management has also become more flexible to further reduce the overall power consumption.

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