Impact of Logic and Circuit Implementation on Full Adder Performance in 50-nm Technologies

In this paper, the authors present the design and characterization of 6 full adder circuits in a 50nm technology. This based on the logic function realized; the adders have been characterized for performance area and power consumption. The impact of sum and carry propagation delays on the performance, power of these systems have been evaluated. This paper has been carried using Micro-wind 3.1 CAD tool with detailed transistor level simulations in a 50nm technology process.