Delft University of Technology
In contrast to planar ICs, during the manufacturing of Three-Dimensional Stacked ICs (3D-SICs) several tests such as pre-bond, mid-bond, post-bond and final tests can be applied. This in turn results into a huge number of test flows/strategies. Selecting appropriate and efficient test flow (for given design and manufacturing parameters such as stack size, die yield, stack yield, etc) is crucial for overall cost optimization. To evaluate the test flows, a case study is performed in which 3D-COSTAR is used to compare the overall cost of producing 3D-SIC using variable fault coverage during the mid-bond tests. In addition, the authors investigate the impact of the logistics cost for various test flows.