Impact of Technology Scaling on Leakage Power in CMOS Circuit Design

Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Topic: Hardware
Format: PDF
Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap for Semiconductors (ITRS). This directly affects the battery operated devices as it has long idle times. Thus by scaling down the threshold voltage has tremendously increased the sub threshold leakage current thereby making the static power dissipation very high. To overcome this problem several techniques has been proposed to overcome this high leakage power dissipation.

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