Low voltage SRAMs are critical for power constrained designs. Currently, the choice of supply voltage in SRAMs is governed by bit cell read static noise margin, writability, data retention etc. However, in the nanometer technology nodes, the choice of supply voltage impacts the reliability of SRAMs as well. Two important reliability challenges for current and future generation SRAMs are gate oxide degradation and soft error susceptibility. The current generation transistors have ultra-thin gate oxides to improve the device performance and they are prone to breakdown due to higher level of electric field stress. In addition, the soft error susceptibility of SRAMs has significantly increased in the nanometer regime.