Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications

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Provided by: International Journal of Computer and Electrical Engineering (IJCEE)
Topic: Hardware
Format: PDF
Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integrity issue in integrated circuits operating at Giga-Hertz (GHz) frequencies. In this paper, the authors propose a method to reduce such via induced signal reflections in on-chip global interconnect lines. They show that the impedance matching can be achieved by the inclusion of an appropriate capacitive load at the junction of the on-chip interconnect line and via. Expressions to determine the capacitance value to be added at via-interconnect junction is derived.
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