Implementation and Comparison of Vedic Multiplier Using Area Efficient CSLA Architectures
Design of area efficient system is one of the most essential parts of research in VLSI. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position was summed and a carry propagated into the next position. In the design of Integrated circuits, area plays a vital role because of increasing the necessity of portable systems. Carry SeLect Adder (CSLA) is a fast adder used in many data-processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification.
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