Implementation and Evaluation of Power Consumption of an Iris Pre-Processing Algorithm on Modern FPGA

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
In this paper, the efficiency and applicability of several power reduction techniques applied on a modern 65nm FPGA is described. For image erosion and dilation algorithms, two major solutions were tested and compared with respect to power and energy consumption. Firstly, the algorithm was run on a General Purpose Processor (GPP) NIOS and then hardware architecture of an Intellectual Property (IP) was designed. Furthermore, IPs design was improved by applying a number of power optimization techniques.
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