Provided by: IRD India
Date Added: Nov 2013
Today, the low power or power efficiency is a key design requirement for nano-meter designs. As technologies have shrunk, leakage power consumption has grown exponentially, thus requiring power reduction techniques. In this paper, the authors focus on the implementation of micro architecture design, verification and place and route layout using latest industry standard tools. The power reduction is done through frequency scaling technique and power gating technique. Logical design (front-end design) is done using Verilog HDL and simulated using Synopsys Verilog Simulator (VCS), version (VCS/E-2011.03).