Implementation of 8-Bit Multiplier in Verilog Using Reversible Logic Gates

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Provided by: International forum of researchers Students and Academician
Topic: Hardware
Format: PDF
Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing, nanotechnology and low-power CMOS design. Low power consumption and smaller area are some of the most important criteria for the high performance systems. Optimizing the speed and area of the multiplier is a major design issue.
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