Implementation of a Transaction Level Assertion Framework in SystemC

Provided by: edaa
Topic: Hardware
Format: PDF
Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as Transaction Level (TL). Since Transaction Level Models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion Based Verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL.

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