Implementation of Adaptive Viterbi Decoder Through FPGA

Provided by: Creative Commons
Topic: Hardware
Format: PDF
The demand for high speed, low power and low cost for Viterbi decoding especially in wireless communication are always required. Thus, the paper presents the design of an adaptive Viterbi decoder that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase the speed. A VHDL description has been adopted to embed the low-power design. The adopted design were coded in VHDL and implemented on a SPARTAN 3.

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