Implementation of Address Generator for WiMAX Deinterleaver on FPGA

In this paper, a low-complexity and novel technique is proposed to implement the address generation circuitry of 2D deinterleaver used in the WiMAX transreceiver using the Xilinx Field-Programmable Gate Array (FPGA). The floor function is associated with the implementation of the steps that are required for the permutations of the incoming bit stream in channel interleaver/deinterleaver for IEEE 802.16e standard, it is very difficult to implement in FPGA. In this paper, the authors develop a simple algorithm along with its mathematical background and eliminate the requirement of floor function and allow low-complexity FPGA implementation.

Provided by: International Journal of Engineering Sciences & Research Technology (IJESRT) Topic: Mobility Date Added: Aug 2015 Format: PDF

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