Implementation of AES-256 Encryption Algorithm on FPGA
The Advanced Encryption Standard (AES) can be programmed in software or built with pure hardware. However, Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. In the implementation of this AES-256 algorithm has a plaintext of 128-bits and key of 256-bits size. The number of rounds of operations in AES-256 is 14. The key generation process of AES 256 is different from other AES algorithms. This paper investigates the AES algorithm with regard to FPGA and the very high speed integrated circuit Verilog Hardware Description language (VHDL). Xilinx 9.2i software is used for simulation and optimization of the synthesizable VHDL code.