Implementation of an Asynchronous Cellular Logic Network as a Co-Processor for a General-Purpose Massively Parallel Array

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
In this paper the authors present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24x60 proof-of concept array integrated circuit has been fabricated in a 0.35μm 3-metal CMOS process and tested. Occupying only 16x8 μm2 the binary wave-propagation cell is used as a coprocessor in a general-purpose processor-per-pixel array that is designed for focal-plane image processing.

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