Implementation of Arbitrary Circuits Using Modified Constant Delay Technique

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Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors perceive pre-evaluation of output before the arrivals of inputs from the preceding stages are ready becomes an added advantage of MCD logic style. Besides adjusting the width of timing window, clock allocation and its distribution are considered as crucial design factors. Power consumption is drastically reduced, but the pre-charge propagation path delay affects the speed performances and limits the Energy Delay Product (EDP) improvement. Using 45nm general purpose CMOS technology, MCD logic is evaluated for single cycle multi-staged circuit block.
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