Implementation of Area Optimized Floating Point Units in Hybrid FPGA

This "Implementation of area optimized floating point unit in hybrid FPGA" is gradually replaces the conventional slower FPUs which have lower speed while computing complex calculations includes digital signal processing. Existing FPGA devices are not optimized for floating point computations, and for this reason, floating point operators consume a significant amount of FPGA resources. The author will try to implement area optimized FPU on a hybrid Field Programmable Gate Arrays (FPGAs) with new feature division, multiplication and addition which is designed with VHDL, synthesized using Xilinx ISE 9.2i Webpack, simulated using ModelSim simulator and then implemented on Xilinx Virtex 2E FPGA.

Provided by: International Journal of Engineering Trends and Technology Topic: Hardware Date Added: May 2013 Format: PDF

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