Power dissipation is a challenging problem for today's System-on-Chips (SoCs) design and test. This paper presents a Low Transition Linear Feedback Shift Register, called LT-LFSR, to reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive pat-terns (fed to a combinational circuit) and consecutive bits (sent to a scan chain). LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures.