Implementation of Carry-Save Adders in FPGA

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Provided by: International Journal of Engineering and Advanced Technology (IJEAT)
Topic: Hardware
Format: PDF
The addition operations can be optimized through a special purpose carry propagation logic in most of the FPGAs. The delay is same for small size operands and this redundant adders require more hardware resources than carry propagate adders. Therefore, carry-save adders are not usually implemented on FPGA devices, although they are very useful in ASIC implementations. In this paper the authors have showed that it is possible to implement redundant adders with a hardware cost close to that of a carry propagate adder.
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